In digital hardware, it is possible to modify the sampling rate of a signal, for example from 400 MHz to 600 MHz, by implementing a digital filter called a polyphase finite-impulse response (FIR) rate change filter (RCF). In a polyphase FIR rate change filter, every output sample y(m) is generated by multiplying the input sample stream with a subset of the filter coefficients (also called phase), and by summing the resulting products. The upsampling and downsampling factors, denoted U and D respectively, are determined by the ratio of the filter input and output sample rates. In the example of a stream being rate changed from 400 MHz to 600 MHz, the U and D factors could be almost any combination of integers that produce a ratio of 1.50. In this example, the upsampling and downsampling factors could be: U=150 and D=100.
In advanced communication systems, very fast data rates are sometimes needed to implement a group of signal processing functions. However, these rates may be too fast to be realized in digital hardware using the existing technologies, such as Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs). Therefore, there is a need for new designs for rate change filters using existing technologies that can increase the effective processing speed for high data rate applications.